Optimisation of charge carrier mobility and lifetime in silicon nanowire solar cells growth by Plasma Enhanced Chemical Vapour Deposition (PECVD) technique at low temperatures.
Carrier mobility and carrier lifetime are two critical charge transport parameters in silicon solar cells, because, they directly impact the electrical conduction in solar cells. The optimisation of these parameters are paramount to the overall performance of solar cells. In this work, a methodology (Experimental and Semi-empirical) is designed to study how to optimise the carrier mobility and carrier lifetime of undoped Schottky junction silicon nanowire solar cells (SiNWs-SC) and the impact of the fabrication temperature on these parameters. The impact of the fabrication and growth conditions on the silicon nanostructures is the first real step in trying to understand these parameters using Plasma Enhanced Chemical Vapour Deposition (PECVD) Method. In this study, silicon nanowires which will be represented in this work as SiNWs were grown on different substrates, such as, Aluminium Doped Zinc Oxide Coated Glass (AZO), P-Silicon and Corning 7059 glass for structural, optical and electrical characterisation. SiNWs were grown using Tin (Sn) catalyst having a mass thickness of 5nm and complete synthesis through the use of Vapour-Liquid-Solid (VLS) bottom-up growth method by PECVD technique was conducted at fabrication temperature ranges between 200oC to 400oC in increments of 25oC intervals while other fabrication and growth conditions remain fixed. From all 9 experiments conducted, SiNWs grown at 3000C and 3250C respectively exhibited more pronounced SiNWs growth evident from the Scanning Electron Microscopy (SEM) images. These SiNWs have morphologies resembling a Spaghetti and Needle like structure respectively. Their respective band gaps are 1.68eV and 1.55eV obtained from optical characterisation technique through Ultraviolet Visible Spectroscopy (UV-Vis). Impedance spectroscopy (IS) technique is applied for the first time to measure the intrinsic carrier concentration (ni) in SiNWs-SC devices by applying DC bias voltages from -0.5V to 0V at an AC voltage of 10mV through a frequency range of 1MHz to 20Hz and the values obtained are in the ranges of 109-1015cm-3 in relation to changes in the fabrication temperature. Each SiNWs-SC device was characterised using IS technique to first find the carrier lifetime (τ) which corresponds to the maximum peak point on the Nyquist plot semicircle and the capacitance (C) value at each these points was derived from the relational RC=τ. The corresponding CV plots were obtained and the 1/C2 against V Mott-Schottky plots was used to calculate the intrinsic carrier concentrations and built-in voltages respectively. Thomas and Caughey's mobility fit model was modified in this work and from this model the carrier mobility (µ) in SiNWs-SC devices was calculated. At low optimization fabrication temperature range between 300oC ≤ ToC ≤ 325oC the average values of τ = (4.96 ± 0.05) µs and µ = (1.5 ± 0.045) cm2/V-s under dark condition are reported respectively.
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