The effect of gate-bias stress and temperature on the performance of ZnO thin-film transistors.

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dc.contributor.authorCross, R. B. M.
dc.contributor.authorDe Souza, M. M.
dc.date.accessioned2010-01-28T09:16:41Z
dc.date.available2010-01-28T09:16:41Z
dc.date.issued2008
dc.identifier.citationCross, R. B. M. and De Souza, M. M. (2008) The effect of gate-bias stress and temperature on the performance of ZnO thin-film transistors. IEEE Transactions on Device and Materials Reliability, 8 (2), pp. 277-282.en
dc.identifier.doihttps://doi.org/10.1109/TDMR.2008.916307
dc.identifier.issn1530-4388
dc.identifier.urihttp://hdl.handle.net/2086/3251
dc.language.isoenen
dc.publisherIEEEen
dc.researchinstituteInstitute of Engineering Sciences (IES)en
dc.titleThe effect of gate-bias stress and temperature on the performance of ZnO thin-film transistors.en
dc.typeArticleen

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