Browsing School of Engineering and Sustainable Development by Subject "negative gate bias stress"

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High-temperature electrical and thermal aging performance and application considerations for SiC power DMOSFETs

Jennings, M.R.; Perez-Tomas, A.; Russell, S.A.O.; Hindmarsh, S.A.; Fisher, C.A.; Mawby, P.A.; Hamilton, Dean (Article)

The temperature dependence and stability of three different commercially-available unpackaged SiC Dmosfets have been measured. On-state resistances increased to 6 or 7 times their room temperature values at 350 °C. Threshold ...