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oai:dora.dmu.ac.uk:2086/132042019-03-20T04:00:51Zcom_2086_2388col_2086_2389

Experimental investigation of carrier mobility degradation in metal oxide semiconductor field effect transistors of high permittivity gate dielectrics Atarah, Samuel Scaling of electronic devices is driven, from the consumption side, by the need for compact electrical products, increase in device speed and from the production side, by lowering of production cost. However, aggressive scaling gives rise, among others, to high gate tunnelling currents in contemporary silicon dioxide (SiO2) based Metal-Oxide- Field Effect Transistors (MOSFETs). SiO2 is therefore expected to be replaced in future technologies with alternative dielectrics. Several dielectrics with high dielectric constants (high-κ) are being studied as candidates for integration into transistors. It is desirable that any dielectric that replaces SiO2 contains as much as possible the electrical properties for which the SiO2 dielectric has been so important in FET technology: high band-offset, low oxide/interface state density and consequently high mobility. However, mobility in transistors with high-κ gate dielectrics is generally lowered compared to their SiO2–based counterparts. Several factors are known to cause mobility degradation in SiO2-based MOSFETs. These include effect of charge scattering centres on the dielectric/Si interface as well as substrate ionized impurities. Also contributing to mobility reduction is phonon scattering, that is, vibration of lattice bonds. In this thesis, samples of high-κ based MOSFETs and MOS capacitors (MOS-C) were experimentally studied for causes of mobility reduction. The study was focused on devices of hafnium silicate gate dielectrics. The nature of interface traps in Hf silicate was completely characterized by determining the interface state density as well as the trap capture cross section. The interface state density levels in the devices was experimentally determined by use of two high resolution techniques: the ac conductance and the charge pumping techniques. Both methods gave similar values of mean interface state density, indicating the accuracy of the experimentally determined mean interface density in the Hf silicate dielectric. Additionally, the ac conductance method established the detailed interface trap distribution profile in Si energy band gap for the Hf silicate dielectric. This study represents the first in depth study of the nature of interface state density in Hf silicate gate dielectrics for CMOS applications x Coulomb limited mobility in Hf silicate based FETs was experimentally quantified by considering the mobility reduction relative to universal mobility values. Using a full quantum mechanical model the mobility limited by Coulomb scattering was calculated considering the physical parameters of the device under study. The calculated and experimentally determined Coulomb limited mobility components were compared using trap charge as the only parameter in the calculation. It was found that a higher trap charge density than determined experimentally was required to match the calculated and measured Coulomb limited mobility in Hf silicate based FETs. The disparity between the theory and the experiment implies that there are other Coulomb scatterers in addition to the interface trap charge. There has been little or no experimental study on the effect of phonons on mobility of Hf silicate based devices, especially, in the ultra thin regime since the first report of successful integration of Hf silicate as a gate dielectric of FETs (A.L.P. Rotondaro, 2002). In this thesis is presented, for the first time, experimental results of phonon-limited mobility in Hf silicate-based FETs by examining the mobility as a function of temperature over a wide range of temperatures below 300 K. Other high-κ based transistors were also studied in order to put the temperature dependence in Hf silicate in perspective. A new model for phonon limited mobility dependence on temperature has been proposed and applied on the experimentally measured data. Compared to the existing model, the new model was found to describe the temperature dependence very well over the entire temperature range studied and over a wide region in the mid-high effective electric field. As stated, scaling introduces difficulties in device characterization. Mobility reduction can not be described by the correct quantity if its evaluation introduces inaccuracies. As such several mobility extraction methods were applied on ultra thin high-κ based FETs to determine the carrier mobility. A comparison of the results (the determined mobility) from all methods showed the disadvantages of each method when applied on high-κ based devices in the ultra thin regime. It was found that the split-CV technique is most xi suitable for (research purposes) studying ultra thin devices – and is thus the preferred method applied throughout the thesis wherever mobility evaluation was required. In all Hf-based dielectrics as this study reveals, have low phonon limited mobility component. Its interface state density was determined to be fairly low compared to the reported values for other high-κ dielectrics and with process refinement, interface charge could be further reduced. Together with a high barrier height, it has already been shown to have a very low gate tunnelling current. All these characteristics make Hf silicate a good alternative to SiO2 in future scaled CMOS applications. De Montfort University 2006 Thesis or dissertation Doctoral PhD en http://hdl.handle.net/2086/13204 https://dora.dmu.ac.uk/bitstreams/7647e42b-8937-4b66-b1e3-f703039f63c0/download 2c8b08093dcb1b79f2ca748a046df87d https://dora.dmu.ac.uk/bitstreams/ab110c1c-7337-486e-9747-a79b39dbd92e/download 78074e3b8a5534add636297b434f123a https://dora.dmu.ac.uk/bitstreams/6bba7fae-07b4-4d2c-9256-116a0953bdf2/download aa3cce147347ef0f777bdb4858e0b7df