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oai:dora.dmu.ac.uk:2086/107872023-09-20T19:30:27Zcom_2086_2388col_2086_2389

Hot carrier degradation in deep submicron n-MOS technologies Manhas, Sanjeev Kumar With the aggressive scaling of MOS devices hot carrier degradation continues to be a major reliability concern. The LDD technologies, which have been used to minimise the hot carrier damage in MOS devices, suffer from the spacer damage causing the drain series resistance degradation, along with the channel mobility degradation. Therefore, in order to optimise the performance and reliability of these technologies it is necessary to quantify the roles of spacer and channel damages in determining their degradation behaviour. In this thesis the hot carrier degradation behaviour of different generations of graded drain (lightly doped, mildly doped and highly doped) n-MOS technologies, designed for 5V, 3V and 2V operation is investigated. The stress time beginning from microseconds is investigated to study how the damage initiates and evolves over time. A technology dependent two-stage degradation behaviour in the measured transconductance with an early stage deviating from conventionally observed power law behaviour is reported. A methodology based on conventional extraction procedure using the L-array method is first developed to analyse the drain series resistance and the mobility degradation. For 5V technologies the analysis of the damage using this methodology shows a two-stage drain series resistance degradation with early stage lasting about lOOms. However, it is seen that the conventional series resistance and mobility degradation methodology fails to satisfactorily predict degradation behaviour of 3V and 2V technologies, resulting in unphysical decreasing extracted series resistance. It is shown that after the hot carrier stress a change in the universal mobility behaviour for channel lengths approaching quarter micron regime has a significant effect on the parameter extraction. A modified universal mobility model incorporating the effect of the interface charge is developed using the FN stress experiments. A new generalised extraction methodology modelling hot carrier stressed device as series combination of undamaged and damaged channel regions, along with the series source drain resistance is developed, incorporating the modified universal model in the damaged channel region. The new methodology has the advantage of being single device based and serves as an effective tool in evaluating. the roles of series resistance and mobility degradations for technology qualification. This is especially true for the deep submicron regime where the conventional extraction procedures are not applicable. Further, the new extraction method has the potential of being integrated into commercial device simulation tools, to accurately analyse the device degradation behaviour in deep submicron regime. De Montfort University 2003 Thesis or dissertation Doctoral PhD en http://hdl.handle.net/2086/10787 https://dora.dmu.ac.uk/bitstreams/7d88bc88-6d39-468c-9d28-0be83af8e650/download 4d7bfee79ecfc7ec4149dc1eee930a8e https://dora.dmu.ac.uk/bitstreams/5ae9d59b-b271-45e5-9f1c-1039eaec3949/download 15be536cc35b26c31250048e9749386d https://dora.dmu.ac.uk/bitstreams/6b4113ce-be96-467b-ad2d-98aa86cdb356/download 762da6eadb7aae4dbaca43ef87ec46a3 621.38152